It is highly recommended that anyone creating a Spartan-6 MCB design thoroughly read the two User Guides (UG388 and. UG416), the MIG Master Answer Record Appendix B: DDR3 memory implementation using the Xilinx® MIG tool. Please refer to the Spartan-6 I/O user guide for more details. Where Can I Learn More? ▫ User Guides. – Spartan-6 FPGA User Guide. • Describes the complete FPGA architecture, including SP605 MIG Design Creation; Revision History; Overview; Spartan-6 Memory Controller Block; MCB Block Diagram; Memory Controller Block Startup; Xilinx SP605 The DDR2 interface follows the pinout and routing guidelines specified in the Xilinx Memory Interface Generator. (MIG) User Guide. The interface supports SSTL18 For more information on the functionality and operation of the MCB, refer to Spartan-6 FPGA Memory Controller User Guide [Ref 1]. FPGA Memory Controller User Guide. [Ref 1] . This chapter describes how to use the MIG tool available in the CORE Generator™ tool or in the Embedded Spartan-6 FPGA Memory Controller User Guide ( UG388 ddr3 XAPP496 Spartan-6 FPGA Memory Controller User Guide mcb circuit diagram mcb design mig ddr