For any queries regarding the NPTEL website, availability of courses or issues in accessing courses, please contact . NPTEL Administrator, IC & SR, 3rd floor IIT Madras, Chennai - 600036 Tel : (044) 2257 5905, (044) 2257 5908, 9363218521 (Mon-Fri 9am-6pm) Email : support@nptel.iitm.ac.in This course is aimed at developing a deep understanding of digital electronic circuits. At the end of the course, one would be able to analyze and synthesize different kind of combinatorial and sequential digital systems for real-world use. INTENDED AUDIENCE : Electronics, Electrical, Instrumentation, Computer Science. NPTEL Syllabus Digital Circuits and Systems - Video course 1. Introduction Sequential Logic systems: Definition of state machines, state machine as a sequential controller; Basic sequential circuits- latches and flip-flops: SR-latch, D-latch, D flip-flop, JK flip-flop, T flip- output values. For a given input combination, a sequential circuit may produce di erent output values, depending on its previous state. * In other words, a sequential circuit has a memory (of its past state) whereas a combinatorial circuit has no memory. * Sequential circuits (together with combinatorial circuits) make it possible to NptelIitm - nptel.ac.in J.J. Shann 6-6 Synchronous Sequential Circuits Clocked seq ckts: most commonly used sync seq ckts — is syn seq ckts that use clock pulses in the inputs of storage elements — has a master-clock generator to generate a periodic train of clock pulses ¾The clock pulses are distributed throughout the system. ¾Storage elements are affected only w/ the arrival of each pulse. Live. •. This course will discuss the basic background of switching circuits, and discuss techniques for mapping the theory to actual hardware circuits. Synthesis and minimization techniques of combinational and sequential circuits shall be discussed in detail. Designing circuits using high-level functional blocks shall also be discussed. Week 11: Asynchronous sequential circuits: analysis and synthesis, minimization, static and dynamic hazards. Week 12: Testing and fault diagnosis in digital circuits: It will be e-verifiable at nptel.ac.in/noc. Only the e-certificate will be made available. Hard copies are being discontinued from July 2019 semester and will not be dispatched; ATPG of sequential circuits: Example Test pattern for the s-a-0 fault ATPG for combinational blocks in sequential circuits require more than one pattern. In this example, the first pattern is a=X, b=0 and clock edge followed by a=1 and b=X. Final pattern is according to combinational ATPG (that sensitize the fault and the design of asynchronous sequential circuits! Not practical for use in synchronous sequential circuits! Avoid to use latches as possible in synchronous sequential circuits to avoid design problems 5-8 SR Latch! A circuit with two cross-coupled NOR gates or two cross-coupled NAND gates! Two useful states:! S=1, R=0 " set state (Q will become The proposed course on digital circuits will cover all the fundamental concepts in digital design. It will primarily focus on the prescribed GATE syllabus for Electronics and Communication Engineering (ECE) specialization. The course will start with the representations of numbers - different number systems and conversion between them The proposed course on digital circuits will cover all the fundamental concepts in digital design. It will primarily focus on the prescribed GATE syllabus