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† Pipelining yields a reduction in the average execution time per instruction. Page 11. Processor. Control. Datapath. Review: Components of a Computer. level pipelining and its affect upon execution performance. machine organization and instruction formats. computer architecture in general.❖ INSTRUCTION PIPELINING​​ Figure 3.1a depicts this approach. The pipeline has two independent stages. The first stage fetches an instruction and buffers it. Schaum's Outline of Theory and Problems of Computer Architecture. Copyright © The McGraw-Hill Companies Learn Instruction pipelining and processing in. Stages of pipelining. Pipeline Stages. RISC processor has 5 stage instruction pipeline to execute all the instructions in the RISC instruction set. The computer is controlled by a clock whose period is such that the fetch and execute steps of any instruction can each be completed in one clock cycle. DEE 1053 Lecture 6: Pipelining. In stitu te of Electronics,. N a tional Chiao Tung University. MIPS Architecture. • Each MIPS instruction take five steps.