Pipelining and ISA Design MIPS ISA designed for pipelining All instructions are 32-bits Easier to fetch and decode in one cycle c.f. x86: 1- to 17-byte instructions Few and regular instruction formats Can decode and read registers in one step Load/store addressing

Household sharing included. Live TV from 60+ channels. No cable box required. Cancel anytime. Pipelining Idealism † Uniform latency Micro-actions Perfectly balanced stages † Identical Micro-actions Must perform the same steps per instruction † Independence of micro-actions across instructions No need to wait for a previous instruction to finish No need to use the same resource at the same time Concept Of Pipelining In Computer Architecture Pdf eline is the continuous and somewhat overlapped movement of instruction to the processor or in the arithmetic steps taken by the processor to perform an instruction. Pipelining is the use of a pipeline. Pipeline Hazards There are situations, called hazards , that prevent the next instruction in the instruction stream from being executing during its designated clock cycle. Hazards reduce the performance from the ideal speedup gained by pipelining. A pipeline diagram A pipeline diagram shows the execution of a series of instructions. In cycle 5, the pipeline is full. Five instructions are being executed simultaneously, so all hardware units are in use. In cycles 6-9, the pipeline is emptying. INSTRUCTION PIPELINING First stage fetches the instruction and buffers it. When the second stage is free, the first stage passes it the buffered instruction. While the second stage is executing the instruction,the first stage takes advantages of any unused memory cycles to fetch and buffer the next instruction. This is called instruction Bubbling the pipeline, also termed a pipeline break or pipeline stall, is a method to preclude data, structural, and branch hazards. As instructions are fetched, control logic determines whether a hazard could/will occur. Instru